This section contains a brief description of the LEON3 SPARC V8 processor implementation developed by Gaisler Research, with an emphasis on information. LEON3 is a synthesizable VHDL model of a bit processor compliant with the SPARC V8 architecture. The processor is highly configurable, and particularly. LEON3 Processor. SPARC V8 instruction set with V8e extensions; Advanced 7- stage pipeline; Hardware multiply, divide and MAC units; High-performance, fully .
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November Learn how and when to remove this template message. It has been designed for operation in the harsh space environment, and includes functionality to detect and correct single event upset SEU errors in all on-chip RAM memories. This page presents the major microprocessors used or to be used in most European space applications. The LEON4 processor has the following features:.
The LEON3 template designs can be configured using a graphical procesor built on tkconfig from the linux kernel. Retrieved from ” http: The fault-tolerance is provided at design VHDL level, and does not require an SEU-hard semiconductor process, nor a custom cell library or special back-end tools.
The LEON4 processor has the following features: Later processors in the LEON series are used in a wide range of designs and are therefore not as tightly coupled with a standard set of peripherals. Hardware iCE Stratix Virtex.
LEON – Wikipedia
SnapGear Linux is a full source package, containing kernel, libraries and application code for rapid development of embedded Linux systems. Retrieved from ” https: It is described in synthesizable VHDL.
BCC includes a small run-time with interrupt support and Pthreads library. Debugging is generally done using the gdb debugger, and a graphical front-end such as DDD procesdor Eclipse.
LEON3 32-bit processor core
It features the following: Views Read Edit View history. LEON3 is also available under a low-cost commercial procesor, allowing it to be used in any commercial application to a fraction of the cost of comparable IP cores.
A single cross-compilation tool-chain is provided which is capable of compiling the kernel and applications for any configuration. The NGMP has the following on-chip functions: Branch prediction, 1-cycle load latency and a 32×32 multiplier results in a performance of 1.
This section and the subsequent subsections focus on the LEON processors as soft IP cores and summarise the main features of each processor version and the infrastructure with which the processor is packaged, referred to as a LEON distribution. The LEON3 processor has the following features:. It features the following:.
LEON3 Processor | eASIC Corporation
The goals have been to detect and tolerate one error in any register without software intervention, and to suppress effects from Leoj3 Event Transient SET errors in combinational logic. Flip-flops proceasor protected by triple modular redundancy and all internal and external memories are protected by EDAC or parity bits. The full source code is available under the GNU GPL license, allowing free and unlimited use for research and education.
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From Wikipedia, the free encyclopedia. The model is highly configurable, and particularly suitable for system-on-a-chip SoC designs. LEON has a dual license model: Aeroflex Gaisler – Device: Another objective was to be able to manufacture in a Single event upset SEU leob3 sensitive semiconductor process. Only netlist distribution is possible. For other uses, see Leon disambiguation.
Archived copy as title Webarchive template wayback links Articles procesaor reliable references from November All articles lacking reliable references Articles containing Spanish-language text Articles with Curlie links. The certification was completed on May 1, This allows new users to quickly define a suitable custom configuration.